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Nanoporous interconnects

 
: Oppermann, H.; Dietrich, L.; Klein, M.; Wunderle, B.

:

Institute of Electrical and Electronics Engineers -IEEE-; VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-:
3rd Electronics System Integration Technology Conference, ESTC 2010. Proceedings. Vol.1 : Berlin, Germany, 13 - 16 September 2010
New York, NY: IEEE, 2010
ISBN: 978-1-4244-8553-6
ISBN: 978-1-4244-8554-3
pp.654-657
Electronics System Integration Technology Conference (ESTC) <3, 2010, Berlin>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Nanoporous gold bumps have been deposited on silicon wafers by electroplating a silver-gold alloy followed by etching the silver. An open-porous cellular structure of gold at meso-scale is left on top of the bumps. For flip chip bonding we found low temperature and low force bonding conditions. The porous interconnects have very promising properties, like compressibility and reduced stiffuess, which should result in higher bond yield and extended reliability.

: http://publica.fraunhofer.de/documents/N-172915.html