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Cap layer and grain size effects on electromigration reliability in Cu/low-k interconnects

: Zhang, L.; Kraatz, M.; Aubel, O.; Hennesthal, C.; Im, J.; Zschech, E.; Ho, P.S.


Institute of Electrical and Electronics Engineers -IEEE-:
International Interconnect Technology Conference, IITC 2010 : 6-9 June 2010, Burlingame, CA (USA)
New York, NY: IEEE, 2010
ISBN: 978-1-4244-7676-3
Art. 5510581
International Interconnect Technology Conference (IITC) <2010, Burlingame/Calif.>
Conference Paper
Fraunhofer IZFP, Institutsteil Dresden ( IKTS-MD) ()

Downstream electromigration (EM) study was performed to investigate the cap layer and the grain size effects on Cu EM reliability for the 45 nm technology node. Four sets of Cu interconnects were examined: large and small grains with and without a CoWP cap placed between the SiCN cap and the Cu lines. Without the CoWP cap, the EM lifetime was reduced by a factor of 1.9 when changing from large to small grain structures and with the CoWP cap, this effect became more significant with EM lifetime reducing from >100x to 24x. Failure analysis showed two types of failure modes with distinct step-like resistance increases and voiding locations in Cu trench lines, reflecting the grain structure effect on void formation and EM statistics. A statistical simulation based on the Monte Carlo method was used to investigate the grain size and cap layer effects. The results were consistent with the experimental observations and the implication on EM reliability for future interconnects was discussed.