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Effects of cap layer and grain structure on electromigration reliability of Cu/low-k interconnects for 45 nm technology node

 
: Zhang, L.; Zhou, J.P.; Im, J.; Ho, P.S.; Aubel, O.; Hennesthal, C.; Zschech, E.

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Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Reliability Physics Symposium, IRPS 2010. Vol.1 : Anaheim, California, USA, 2 - 6 May 2010
New York, NY: IEEE, 2010
ISBN: 1-4244-5430-1
ISBN: 978-1-4244-5430-3 (print)
ISBN:
pp.581-585
International Reliability Physics Symposium (IRPS) <48, 2010, Anaheim/Calif.>
English
Conference Paper
Fraunhofer IZFP, Institutsteil Dresden ( IKTS-MD) ()

Abstract
The effects of cap layer and grain structure on electromigration (EM) reliability of Cu/low-k interconnects were investigated for the 45 nm technology node. Compared to the SiCN cap only, the CoWP capped samples showed a 40x lifetime improvement with a small lifetime variation (=0.34) at the M1 level. By tuning the process parameter, Cu lines of two different grain sizes were fabricated at the M2 level for both with and without the CoWP cap. The EM results showed that, for both caps, the Cu lines with the large grain structure had a longer EM lifetime compared with the small grain structure, and the EM enhancement of the metal cap was reduced for the small grain structure. Failure analysis revealed two failure modes for the SiCN cap, with void formation either at the via corner or in the trench away from the via; on the contrary, voids mostly formed several microns away from the via for the large grain CoWP cap. The difference in voiding locations for the two caps was a ttributed to the different interfacial mass transport rate. Implications of scaling effect on EM reliability were also discussed.

: http://publica.fraunhofer.de/documents/N-172834.html