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Micro structure analysis for system in package components - novel tools for fault isolation, target preparation, and high-resolution material diagnostics

 
: Petzold, M.; Altmann, F.; Krause, M.; Salzer, R.; Schmidt, C.; Martens, S.; Mack, W.; Dömer, H.; Nowodzinski, A.

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Preprint urn:nbn:de:0011-n-1725964 (4.1 MByte PDF)
MD5 Fingerprint: f4244bf1c8bf066ffcc736cfec574fa4
© 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Created on: 20.4.2013


IEEE Components, Packaging, and Manufacturing Technology Society; Electronic Industries Alliance -EIA-:
60th Electronic Components and Technology Conference, ECTC 2010. Proceedings. Part 2 : 1-4 June 2010, Las Vegas, NV, USA
New York, NY: IEEE, 2010
ISBN: 978-1-4244-6410-4
ISBN: 978-1-4244-6412-8
pp.1296-1302
Electronic Components and Technology Conference (ECTC) <60, 2010, Las Vegas/Nev.>
English
Conference Paper, Electronic Publication
Fraunhofer IWM ()

Abstract
In this paper we introduce novel tools for an improved failure analysis process flow for complex packaged microsystems. This failure analysis process flow starts with a non-destructive defect localization using an improved Lock-In Thermography (LIT). After fault isolation, a highly efficient target preparation can be performed using crosssectioning by combined pulsed-laser ablation and highcurrent Focused-Ion-Beam (FIB) milling in a specifically modified FIB device. The sample quality achieved is high enough to enable improved high-resolution material analysis of cross-sectioned structures using Scanning Electron Micrography (SEM) and Electron Back-Scatter Diffraction (EBSD), particularly for the analysis of highly resistive bonding interconnects, intermetallic compound identification, and texture analysis. To illustrate the complete workflow of the approach, a failure analysis of a vertically integrated microsystem using a microinsert technology is described. The parti cular benefit of each step is compared to conventional approaches in failure analysis. In addition, the potential of the new failure analysis methodology for future applications using System in Package (SiP) technologies is highlighted.

: http://publica.fraunhofer.de/documents/N-172596.html