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Three-valued automated reasoning on analog properties

: Gentilini, R.; Schneider, K.; Dreyer, A.


Association for Computing Machinery -ACM-, Special Interest Group on Design Automation -SIGDA-; IEEE Circuits and Systems Society:
ACM Great Lakes Symposium on VLSI 2007. Proceedings : Stresa, Lago Maggiore, Italy, March 11 - 13, 2007
New York: ACM, 2007
ISBN: 978-1-595-93605-9
Great Lakes Symposium on VLSI (GLSVLSI) <17, 2007, Stresa>
Conference Paper
Fraunhofer ITWM ()

We deal with the problem of designing suitable languages for the modeling and the automatic verification of properties over analog circuits. To this purpose, we suitably enrich classical temporal logics with basic formul\ae allowing to model arbitrary functions relating analog variables. We show how to automatically check the resulting CTLf formulæ on analog circuits. In particular, we rely on interval arithmetic methods and we extend to the analog context a number of techniques for the abstraction and the verification of digital systems, based on three-valued temporal logics.