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High efficiency silicon solar cells with ink jetted seed and plated grid on high sheet resistance emitter

 
: Ebong, A.; Rounsaville, B.; Cooper, I.B.; Tate, K.; Rohatgi, A.; Glunz, S.; Hörteis, M.; Mette, A.; Gundermann, M.

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Fulltext urn:nbn:de:0011-n-1720467 (1.4 MByte PDF)
MD5 Fingerprint: 3b48a1ebcaaf96846574dd0943b43ff1
© 2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Created on: 4.8.2012


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Electron Devices Society:
35th IEEE Photovoltaic Specialists Conference, PVSC 2010. Vol.2 : Honolulu, Hawaii, USA, 20 - 25 June 2010
Piscataway/NJ: IEEE, 2010
ISBN: 978-1-4244-5890-5
ISBN: 978-1-4244-5891-2
ISBN: 978-1-4244-5892-9
pp.1363-1367
Photovoltaic Specialists Conference (PVSC) <35, 2010, Honolulu/Hawaii>
English
Conference Paper, Electronic Publication
Fraunhofer ISE ()

Abstract
Fine and tall grid lines on high sheet resistance emitter can increase the efficiency of silicon solar cells by reducing the shadow loss and improving the blue response. However, current screen printing pastes are neither able to provide the adequate line geometry nor make good ohmic contact to high sheet resistance emitter. This paper uses a combination of inkjet printing and light induced plating of silver to solve both problems. The ink jetting of grid lines is used to write 38 m wide and 4 m tall seed lines. These grid lines grow to 65 m wide and 20-25 m tall after light induced plating of silver. The silver plating solution penetrates the entire contact region underneath the grid lines to reduce the PbO in the glass layer to Pb metal in addition to plating the silver crystallites underneath. This lowers the contact resistance. Prolonged plating builds the line height to reduce the line resistance. A combination of low contact and line resistances produced fill fact or of 79.2% on 95-/sq emitter. This resulted in 239-cm2 Cz silicon solar cell efficiencies up to 18.7% with an average of 18.4%.

: http://publica.fraunhofer.de/documents/N-172046.html