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A successive approximation A/D converter with 16bit 200kS/s in 0.6m CMOS using selfcalibration and low power techniques

: Neubauer, H.; Desel, T.; Hauer, H.

8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001. Vol.2 : 02 Sep 2001-05 Sep 2001, Malta
Piscataway: IEEE, 2001
ISBN: 0-7803-7057-0
International Conference on Electronic, Circuits, and Systems (ICECS) <8, 2001, Malta>
Conference Paper
Fraunhofer IIS ()

A low power (6.8 mW) 5 V analog 2.7 V digital 16 bit 200 kS/s charge redistribution self calibrating successive approximation (SA) Analog/Digital Converter (ADC) is presented. The device is implemented in a 0.6 m CMOS technology with 2 mm2 active area. This multi purpose ADC macro is intended to be integrated with digital signal processing on ASICs. The SA principle permits input multiplexing and sampling at discrete times.