Publica
Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten. Low-complexity FPGA implementation of Volterra predistorters for power amplifiers
| IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, PAWR 2011 : 16-19 Jan. 2011, Phoenix
Piscataway, NJ: IEEE, 2011
ISBN: 978-1-4244-8416-4 (print)
pp.41-44 |
| IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR) <2011, Phoenix> |
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| English |
| Conference Paper |
| Fraunhofer HHI () |
Abstract
In this paper we present a FPGA design of a digital predistorter (DP) for power amplifiers (PAs) regarding memory effects. As model description the baseband Volterra series are utilized. A reduction of Volterra coefficients can be achieved using their symmetry properties. An advantage of our DP approach is a direct offline model identification, without need to analytically or iteratively calculate a PA model inverse. The DP implementation is very flexible and saves FPGA ressources. Our simulation and measurement results show a good linearization performance applying simple Volterra model structures. DP with and without memory are compared.