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Virtual prototyping in microelectronics and packaging

 
: Rzepka, S.; Dudek, R.; Vogel, D.; Michel, B.

Kowalik, P. (Hrsg.) ; Components, Packaging and Manufacturing Technology Society -CPMT-; International Microelectronics and Packaging Society -IMAPS-, Poland Chapter:
XXXIII international conference IMAPS - CPMT IEEE Poland. Proceedings. CD-ROM : 21 - 24 September 2009, Pszczyna, Poland
Gliwice: Silesian Univ. of Technolog, 2009
ISBN: 978-83-91770-17-7
pp.316-325
International conference IMAPS - CPMT IEEE Poland <33, 2009, Pszczyna>
English
Conference Paper
Fraunhofer ENAS ()

Abstract
In the paper, the current state of the art in virtual prototyping is surveyed by reviewing three examples of its application in microelectronics and packaging. First, the thermo-mechanical risk of 3-D through silicon via structures is assessed while their design was still under development. Hence, the first real samples could directly be made based on an improved design avoiding months of experimental tests before. Secondly, a stochastic analysis has shown the process of flip chip soldering onto unsupported organic substrates to lack on robustness inherently. Virtual prototyping stopped months of fruitless experiments and redirected the efforts to the revision of the process concept eventually increasing the fabrication yield to acceptable magnitudes. Thirdly, details of methodology improvements are highlighted. Key to the boost in prediction accuracy has been a seamless interaction between simulation and experimental analyses. Weak point identification, calibration, and validation of the models was performed based on dedicated tests and advanced analytical tools. It allowed lowering the inaccuracy of BGA thermal cycle lifetime prediction down to the magnitude of standard deviation in the regular sample tests. In product development, virtual prototyping can now replace time consuming experiments without loosing accuracy.

: http://publica.fraunhofer.de/documents/N-151457.html