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Adaptive multiprocessor system-on-chip architecture: New degrees of freedom in system design and runtime support

: Göhringer, D.; Hübner, M.; Becker, J.


Hübner, M.:
Multiprocessor System-on-Chip: Hardware Design and Tool Integration
New York: Springer Science+Business Meda, 2011
ISBN: 978-1-4419-6459-5
ISBN: 978-1-4419-6460-1
Book Article
Fraunhofer IOSB ()

The requirements to a processor, in terms of its characteristics like e.g. RISC, CISC, bitwidth, instruction set and to the communication and memory bandwidth differ for each application to be implemented. Furthermore, the required characteristic can be different at runtime, because the application has to react to the demands of the environment. Image processing is a good example for this scenario, because this application domain needs to adapt, depending on the content of the camera frames. Integrated e.g. in a robot, the time variant requirements to the image processing applications are obvious. Sometimes gestures, obstacles, moving targets etc. needs to be detected within a high resolution picture provided by one or more cameras. For such applications a novel runtime adaptive multiprocessor System-on-Chip (RAMPSoC) was invented to provide an adaptive hardware architecture at design- and at runtime. This way, new degrees of freedom in system design and runtime support are provided. To program such a flexible multiprocessor system an efficient design methodology is of high importance in order to hide the complexity of the underlying hardware. In addition, a runtime operating system is needed to handle the resource management and the runtime scheduling of the applications. In this chapter the hardware architecture, the de-sign methodology and the runtime operating system of RAMPSoC will be de-scribed. Furthermore, a brief overview about reconfigurable computing and dynamic and partial reconfiguration will be given.