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Vertical Design of InN Field Effect Transistors

 
: Granzner, R.; Kittler, M.; Schwierz, F.; Polyakov, V.M.

:

Institute of Electrical and Electronics Engineers -IEEE-:
European Solid-State Device Research Conference, ESSDERC 2010. Proceedings : 14-16 Sept. 2010, Sevilla, Spain
New York, NY: IEEE, 2010
ISBN: 978-1-4244-6658-0
ISBN: 978-1-4244-6661-0
pp.428-431
European Solid-State Device Research Conference (ESSDERC) <40, 2010, Seville>
European Solid-State Circuits Conference (ESSCIRC) <36, 2010,
English
Conference Paper
Fraunhofer IAF ()

Abstract
The vertical design of indium nitride field effect transistors is investigated by numerical simulation. To this end, the Schrödinger equations for electrons and holes and Poisson's equation are solved self-consistently. It is shown that in several layer sequences simultaneously two-dimensional electron and hole gases are formed in the InN channel. It is demonstrated that because of the high unintentional n-type doping only thin InN layers are useful for proper transistor operation. Strain in the InN layer leads to the formation of parasitic hole channels which can dramatically deteriorate transistor characteristics. Finally it is shown that thin relaxed InN channels on GaN or AlInN buffers are a viable option for InN transistors.

: http://publica.fraunhofer.de/documents/N-146152.html