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1989
Conference Paper
Titel
Signal processor SIPRO23 with minimized overhead
Abstract
The architecture of SIPRO23 was designed with special attention to the problems of data addressing in DSP (digital signal processing) algorithms in order to achieve increased throughput. The realization of SIPRO23 with 2- mu m CMOS technology requires 121 mm2 of chip area. The cycle time is estimated on the basis of simulations to be 130 ns. The derivation of the architecture and the processor components from DSP algorithms is explained.
Language
English