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A low-power continous-time incremental 2nd-order-MASH Sigma Delta-modulator for a CMOS imager

: Uhlig, J.; Schuffny, R.; Neubauer, H.; Hauer, J.; Haase, J.


Institute of Electrical and Electronics Engineers -IEEE-:
16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009 : Yasmine Hammamet, Tunisia, 13 - 16 December 2009
Piscataway/NJ: IEEE, 2009
ISBN: 978-1-4244-5090-9
ISBN: 978-1-4244-5091-6
International Conference on Electronics, Circuits and Systems (ICECS) <16, 2009, Yasmine Hammamet>
Conference Paper
Fraunhofer IIS ()

This paper presents a novel Sigma Delta-modified MASH architecture (MMA) for a CMOS imager. This architecture makes use of a 1st-order incremental continuous-time sigma-delta modulator with 1.5-bit internal quantizer. It shows key benefits regarding efficient decimation and reduced circuit complexity compared to conventional Sigma Delta-architectures. Theory of operation, impact of non-idealities, implementation issues and benefits of the new architecture are depicted. The implementation of the MMA in an 180nm CMOS-Process and simulation results are presented.