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Parallel architecture for VLSI implementation of a 2-dimensional discrete cosine transform for image coding

: Liebsch, W.

IEE Electronics Division:
Third International Conference on Image Processing and its Applications : 18 - 20 July 1989; venue: University of Warwick, UK
London: IEE, 1989 (IEE conference publication 307)
ISBN: 0-85296-382-3
International Conference on Image Processing and Its Applications <3, 1989, Coventry>
Conference Paper
Fraunhofer HHI ()
cmos integrated circuits; codecs; computerised picture processing; digital signal processing chips; parallel architectures; vlsi; image processing chip; dsp; 2-dimensional discrete cosine transform; image coding; parallel architecture; image data compression; advanced television; HDTV; cmos technology; 80 mhz

A new efficient parallel architecture is presented for high-speed two-dimensional discrete cosine transform (DCT) for image data compression with a block size of 8*8 picture elements. This circuit is applicable in advanced television and HDTV systems working at video sampling-rate up to 80 MHz and can be realized in CMOS technology as a single VLSI component.