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A high-speed adaptive image DCT coder with parallel architecture for VLSI implementation

: Liebsch, W.

Torres, L. ; European Association for Signal Processing -EURASIP-:
Signal processing V. Theories and applications. Proceedings of EUSIPCO-90, Fifth European Signal Processing Conference : Barcelona, Spain, September 18-21, 1990
Amsterdam: Elsevier, 1990
ISBN: 0-444-88636-2
European Signal Processing Conference (EUSIPCO) <5, 1990, Barcelona>
Conference Paper
Fraunhofer HHI ()
cmos integrated circuits; computerised picture processing; data compression; high definition television; parallel architectures; transforms; video signals; vlsi; high-speed adaptive image dct coder; parallel architecture; discrete cosine transform; bit rate reduction; distributed coder functions; symmetry; dct matrix; internal clock rate; advanced television systems; HDTV; cmos; 80 hz

A new efficient discrete cosine transform (DCT) for bit rate reduction of video signals is presented. The design combines a parallel two-dimensional DCT architecture with distributed coder functions. By taking advantage of the symmetry in the DCT matrix, the internal clock rate is reduced to a factor of 4. This circuit is applicable in advanced television systems (HDTV) operating at video sampling rate up to 80 MHz and can be realized in CMOS technology as a single VLSI component. This architecture utilizes the advantage of parallel and distributed arithmetic to achieve high-speed performance.