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A controllable mechanism of forming extremely low-resistance nonalloyed ohmic contacts to group III-V compound semiconductors

: Stareev, G.; Kunzel, H.; Dortmann, G.


Journal of applied physics 74 (1993), No.12, pp.7329-56
ISSN: 0021-8979
ISSN: 1089-7550
Journal Article
Fraunhofer HHI ()
annealing; contact resistance; doping profiles; gallium arsenide; gold; iii-v semiconductors; indium compounds; ion beam effects; metallisation; ohmic contacts; platinum; rapid thermal processing; semiconductor epitaxial layers; semiconductor-metal boundaries; silicon; surface treatment; titanium; tunnelling; zinc; surface cleaning; epitaxial layers; as-deposited sample; annealed sample; tunneling metal-semiconductor contacts; low-resistance nonalloyed ti/pt/au ohmic contacts; iii-v compound semiconductors; doping levels; electrical parameters; P-InGaAs Zn; N-InGaAs; metallization scheme; Si-doped N-InAs; ion-beam cleaning; postdeposition annealing; ion damage defects; depletion depth; 40 sec; 60 ev; InGaAs; InAs; GaAs; Ti; Pt; Au

This work refers basically to the detailed understanding of the natural phenomena in real tunneling metal-semiconductor contacts. A mechanism of forming extremely low-resistance nonalloyed Ti/Pt/Au ohmic contacts to a variety of III-V compound semiconductors, e.g., InGaAs, InAs, and GaAs, is presented. Epitaxial layers of either type with different doping levels ranging from 1*1019 to 2*1020 cm-3 were employed in order to determine electrical parameters that guarantee pure tunneling behavior of the contacts. Ti/Pt/Au contacts formed on p-InGaAs Zn doped to 1*1020 cm-3 and on n-InGaAs Si doped to 5*1019 cm-3 yielded a specific contact resistance of 4.8*10-8 and 4.3*10-8 Omega cm2, respectively. The same metallization scheme applied to 4*1019 cm-3 Si-doped n-InAs gave a specific contact resistance of 1.7*10-8 Omega cm2 for the as-deposited and annealed samples. An extremely low value of 2.8*10-8 Omega cm2 was evaluated for contacts on p-GaAs doped with Be to 2*1020 cm-3. The contact properties are discussed in relation to the effect of ion-beam cleaning and postdeposition annealing. Of particular concern was the cleaning of the semiconductor surface with low-energy (60 eV) Ar+ ions for 40 s prior to the metallization process. This opens also the possibility to investigate ion damage defects and trap-assisted increase of the depletion depth. The contact design was based on the concept that the detrimental influence of the ion beam on the semiconductor properties can be neutralized with a proper annealing. It has been demonstrated that even very rapid thermal processing for 1 s at elevated temperatures was sufficient to restore the stoichiometry in the As-depleted subsurface layer arising as a result of ion damage. The fabrication sequences used provide formation of intimate contacts without interfacial films and carrier compensation effects. Optimal processing conditions have been empirically established that stimulate substantially the ohmic behavior of the contacts. It was possible to achieve an absolute control over the contact formation mechanism without crucial adjustment of annealing parameters. Closer examination of the temperature dependence of the contact resistances reveals a good agreement with the theoretical approach based on the tunneling model. Metallurgical studies of the contacts confirm their unreacted, abrupt metal-semiconductor configurations if optimal annealing temperatures are used. Experimental evidence manifests a definite relationship between electrical properties and interfacial compositional modifications affected by different forming conditions. The trend for structural changes occuring at annealing temperatures above the optimal ones was found to be in correlation with the chemical reactivity of III-V compounds. The observed thermal stability of the contacts can be fully explained in this way. In contrast to chemical precleaning the controllable elimination of interface inhomogeneities during ion etching results in contacts with improved homogeneity and uniformity. The demonstrated universality and reliability make the fabrication technique suitable to meet specific needs of modern semiconductor devices.