Abstract
In this paper, we investigate the specific impact of an additional silicon oxide layer (sealing oxide) on top of the charge-trap nitride on the electrical performance of small dimension and large TANOS charge-trapping (CT) memory cells. We observe a significant improvement in charge retention on both our target 48-nm NAND TANOS cells and on large 5 µm long and wide memory cells. However, erase performance is partially degraded by this additional silicon dioxide top-dielectric layer. The presented intrinsic CT stack retention for 3.5-nm sealing oxide, which is visible on large cell structures, clearly shows the potential for multilevel cell operation. We further identified trapping in the Al2O3 states of the blocking dielectric to improve the program and erase performance of conventional TANOS memory cells. However, detrapping from these trap states was found to be the root cause of insufficient retention.