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Hardware implementation of a motion-compensating format converter

: Hahn, M.; Wolf, S.; Talmi, M.; Karl, M.


Journal of electronic imaging 4 (1995), No.3, pp.270-277
ISSN: 1017-9909
Journal Article
Fraunhofer HHI ()
digital signal processing chips; field programmable gate arrays; high definition television; image classification; interpolation; motion compensation; motion estimation; television standards; video signal processing; vlsi; motion-compensated 3-d interpolation; hardware implementation; tv-interlaced to HDTV-interlaced real-time format converter; hierarchical block matching; reliability checking; picture classification algorithms; vlsi chips; digital signal processors; field-programmable gate arrays; video processing

The realization of a TV-interlaced (TVI) to HDTV-interlaced (HDI) real-time format converter for studio applications is described. The conversion is performed by motion-compensated 3-D interpolation. The estimation of motion is based on hierarchical block matching. Reliability checking of motion vectors is applied to achieve high picture quality. Furthermore, various picture classification algorithms are utilized to improve the reliability of motion vectors. This format converter has been developed using specially designed VLSI chips, digital signal processors, and field-programmable gate arrays for the reduction of hardware. The special VLSI chips have been developed using semicustom and full-custom design techniques. Besides employment within the format converter they are suitable for various applications in video processing.