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Challenges for multi-scale modeling of multiple failure modes in microelectronics

 
: Auersperg, J.; Wunderle, B.; Dudek, R.; Walter, H.; Michel, B.

:

Braunschweig, B. ; European Federation of Chemical Engineering -EFCE-, Working Party on Computer Aided Process Engineering:
18th European Symposium on Computer Aided Process Engineering, ESCAPE 2008 : Held in Lyon, France, June 1 - 4, 2008
Amsterdam: Elsevier, 2008 (Computer-aided chemical engineering 25)
ISBN: 0-444-53227-7
ISBN: 978-0-444-53227-5
pp.15
European Symposium on Computer Aided Process Engineering (ESCAPE) <18, 2008, Lyon>
European Federation of Chemical Engineering, Working Party Computer Aided Process Engineering (Event) <40, 2008, Lyon>
English
Conference Paper
Fraunhofer ENAS ()
Fraunhofer IZM ()

Abstract
Design studies of electronics components on the basis of parameterized Finite Element Models and DoE/RSM-approaches (Design of Experiments/Response Surface Methods) are more and more performed for optimizations at early phases of the product development process. That is why electronics components especially in the field of RF (Radio Frequency), optoelectronics, high temperature and power applications are often exposed to extreme thermal environmental conditions, mechanical shock and vibrations. However, a continuous industry drive for miniaturization and function integration forces the development of eature sizes down to the nanometer regime. Simultaneously, the well known thermal expansion mismatch problem of the several materials, residual stresses generated by several steps of the manufacturing process and various kinds of inhomogeneity attribute to interface delamination, chip cracking and fatigue of interconnects, in particular. The applied methodologies typically base on classical stress/strain strength evaluations or/and life time estimations of solder interconnects using modified Coffin-Manson approaches. Recent studies show also how the evaluation of mixed mode interface delamination phenomena, classical strength hypotheses along with fracture mechanics approaches and thermal fatigue estimation of solder joints can simultaneously be taken into account. Over and above that, new materials will be introduced especially in Back-end of line (BEoL) layers of advanced Cu/Low-k 90, 45, ..., 22 nanometer CMOS (Complementary Metal-Oxide Semiconductor) technologies. So, black diamond-I or black diamond-II as new materials are increasingly porous and interconnect materials or new functional layers come up as nano-particle filled high-tech compounds. Thus, it is to be checked whether it can be handled as homogeneous materials anymore. For sure, this will have most important impacts on the thermo-mechanical performance of the total IC (Integrated Circuit) tack. The problems appearing during packaging of CMOS-ICs at least showed that IC and package reliability are strongly interacted. Thus, the challenge for simulations in this field is not only the wide range of structural dimensions but also, the different approaches that have to be combined: Molecular or atomistic level simulations and "conventional" Finite Element Analysis (FEA) with global-local modeling, substructuring as well as fracture and damage mechanics, cohesive zone models, viscoelasticity, plasticity and creep of homogeneous constitutive models. Furthermore, it is known that multiple failure modes competitively act simultaneously wherefore, design optimizations have to incorporate all failure modes that are essential for the overall reliability. Moreover, considering that variables of the simulation models are naturally stochastic parameters leads to the consequence that all results show also scattering.
First steps towards robust designs show the potential of the utilized FEA-based RMS/DOE approach to evaluate the thermo-mechanical reliability of various electronics assemblies in a more complex way giving at the same time a more solid basis for design optimizations.

: http://publica.fraunhofer.de/documents/N-134029.html