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Chipset for a single-board MPEG-2 SSP@H-1440L HDTV-decoder

 

Ninomiya, Y.:
Signal processing of HDTV, VI : Proceedings of the International Workshop on HDTV '94, Turin, Italy, October 26 - 28, 1994
Amsterdam: Elsevier, 1995
ISBN: 0-444-82283-6
International Workshop on HDTV <6, 1994, Torino>
English
Conference Paper
Fraunhofer HHI ()
cable television; digital signal processing chips; digital television; direct broadcasting by satellite; hardware description languages; high definition television; motion compensation; source coding; television broadcasting; television reception; video equipment; video signal processing; vlsi; chipset; single-board mpeg-2 HDTV decoder; vlsi realization; mpeg-2 conformant hierarchical video decoder; high-1440 level; heinrich-hertz-institut; hierarchical digital television transmission; HDTVt; tv-HDTV compatibility; spatial scalability; terrestrial broadcasting; logic synthesis; vhdl; snr scalability; integrated hardware solution; bistro; transport stream reception; idct; mofa; upconversion; global frame store addressing

Abstract
This paper presents the VLSI realization of an MPEG-2 conformant hierarchical video decoder based on the spatially scalable profile at the High-1440 Level (SSP@H-14L). The decoder is built at the Heinrich-Hertz-Institut (HHI) as part of the ongoing joint R&D project "Hierarchical digital television transmission" (HDTVT) and will be demonstrated during the international exhibition IFA 1995 in Berlin. The project proposes a compatible approach to HDTV (TV-HDTV compatibility due to spatial scalability). Terrestrial broadcasting with graceful degradation and portable reception (through spatial and SNR scalability) are supported besides the less demanding cable and satellite scenarios. Two chips are currently under development to achieve an integrated hardware solution for the hierarchical MPEG-2 video source decoder. The first chip, BISTRO, incorporates all functions from transport stream reception up to the IDCT. The second chip, MOFA, is performs upconversion, motion compensation, global frame store addressing and digital output of the decoded data. The design concept uses logic synthesis from VHDL. The design is verified through automatic comparison with the results from a high-level MPEG-2 reference program. An on-board DSP supports board self-test and serves for system monitoring during field trials. The complete hierarchical HDTV video decoder fits on one single PCB.

: http://publica.fraunhofer.de/documents/N-13347.html