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Test and monitoring of an HDTV MPEG-2 video decoder using the TMS320C40


5th International Conference on Signal Processing Applications & Technology 1994. Proceedings. Vol.1 : Dallas, Texas, USA, October 18 - 21, 1994
Waltham/Mass.: DSP, 1994
International Conference on Signal Processing Applications & Technology (ICSPAT) <5, 1994, Dallas/Tex.>
Conference Paper
Fraunhofer HHI ()
built-in self test; digital signal processing chips; high definition television; telecommunication equipment testing; television standards; video coding; video equipment; HDTV mpeg-2 video decoder; tms320c40; test strategy; spatially scalable profile; high-1440 level; sspath-14l; heinrich-hertz-institut; hierarchical digital tv-transmission; HDTVt; mpeg-2 standard; decoding parameters; non defined states; visible decoding errors; i/o capabilities; functional built-in self-test; f-bist; pcb-development time

This paper reports the realization of a test strategy for a hierarchical HDTV MPEG-2 video decoder based on the spatially scalable profile at High-1440 Level (SSPatH-14L) currently under development at the Heinrich-Hertz-Institut (HHI) within the ongoing joint R&D project "hierarchical digital TV-transmission" (HDTVT) and which will be demonstrated during the international exhibition IFA 1995 in Berlin. Due to the large variety of parameters in the MPEG-2 standard a full test of the functionality of the MPEG-2 decoder is not possible during the development. There is a certain possibility that some combinations of decoding parameters cause non defined states in the decoder and visible decoding errors. The cause of those errors has to be pinpointed to aid further improvements of the decoder. In this paper a test strategy is proposed which utilizes the computing power and the I/O capabilities of the TMS320C40. The strategy is based on a functional built-in self-test (F-BIST) approach. The decoding process is observed by the DSP and possible problems are identified. The usage of a DSP provides a high degree of flexibility as well as a relatively small amount of external hardware on board, thus reducing PCB-development time.