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Impact of lithography variations on advanced CMOS devices

: Lorenz, J.; Kampen, C.; Burenkov, A.; Fühner, T.


Institute of Electrical and Electronics Engineers -IEEE-:
VLSI-TSA 2009, International Symposium on VLSI Technology, Systems, and Applications : 27-29 April 2009, Hsinchu, Taiwan
New York, NY: IEEE, 2009
ISBN: 978-1-4244-2784-0
ISBN: 978-1-4244-2785-7
ISSN: 1930-8885X
International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) <2009, Hsinchu>
Conference Paper
Fraunhofer IISB ()
process variation; lithography simulation; process simulation; CMOS devices; variation-tolerant process flow; device architecture

Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.