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Transmitting TLM transactions over analogue wire models

: Schulz, S.; Becker, J.; Uhle, T.; Einwich, K.; Sonntag, S.

Postprint urn:nbn:de:0011-n-1252004 (629 KByte PDF)
MD5 Fingerprint: 83a07d573a34c2fa8dcb6329692cc511
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Created on: 23.6.2012

Association for Computing Machinery -ACM-, Special Interest Group on Design Automation -SIGDA-; IEEE Computer Society; IEEE Solid-State Circuits Society:
Design, Automation and Test in Europe 2010. Proceedings : ICC, Dresden, Germany, 8-12 March, 2010
New York, NY: IEEE, 2010
ISBN: 978-1-4244-7054-9
ISBN: 978-3-9810801-6-2
Design, Automation and Test in Europe Conference (DATE) <2010, Dresden>
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
SystemC AMS

Nowadays digital systems have very high switching frequencies. Hence analogue effects can have a serious impact on data transmissions of connected modules in System-on-Chip (SoC) designs. The implications include attenuation, delay, and others which have to be considered as important effects. However, analogue technology models comprise too many details to be usable at system level as the simulation time would be far to high compared to traditional Transaction Level Modelling (TLM) models. In this paper we illustrate different aspects of using analogue line models as a transmission method for transactions between TLM models. This includes the introduction of analogue signal paths for TLM models and how to avoid the simulation time penalty of analogue technology models. We show how we can even use this approach to apply analogue effects to electronic system level (ESL) performance evaluations by further reducing the amount of details of the analogue effects.