Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

A 3-D packaging concept for cost effective packaging of MEMS and ASIC on wafer level

 
: Baumgartner, T.; Töpper, M.; Klein, M.; Schmid, B.; Knödler, D.; Kuisma, H.; Nurmi, S.; Kattelus, H.; Dekker, J.; Schachler, R.

International Microelectronics and Packaging Society -IMAPS-, Italian Chapter; Institute of Electrical and Electronics Engineers -IEEE-:
EMPC 2009, 17th European Microelectronics and Packaging Conference & Exhibition. CD-ROM : June 15th-18th, 2009 , Rimini, Italy
New York, NY: IEEE, 2009
ISBN: 0-615-29868-0
ISBN: 978-0-615-29868-9
ISBN: 978-1-4244-4722-0
pp.7-11
European Microelectronics and Packaging Conference and Exhibition (EMPC) <17, 2009, Rimini>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Heterogeneous integration bridges the gap between nanoelectronics and its derived applications. Currently MEMS and their signal conditioning ASICs are produced and packaged at different industry sectors (different jabs). To reduce costs and enhance Yield and performance at the same time this quite expensive way of packaging has to be modified. This paper presents a different pack-aging concept. It uses standard redistribution layer technology (RDL) to package thinned chips on a full wafer substrate e.g. thinned ASIC chips on a MEMS wafer. For this approach no Through Silicon Vias (TSV) are needed Standard chips can be used without redesign. Only Known Good Dies (KGDs) are packaged with the cost benefit of wafer level technology. At the starting point for this type of packaging both ASIC and MEMS chips are still parts of full wafers. The wafer with the larger sized chips (e.g. MEMS chips) is used as a substrate for the further process steps. The wafer with the smaller sized chips (e.g. ASIC chips) is thinned down on wafer level to a thickness of 10 mu m to 40 mu m and diced. These thinned chips are glued onto the base wafer with a polymer layer (BCB from Dow Chemical). The polymer has been deposited and structured before gluing the next chip on top. After placement of the thinned chips the wafer is again coated with BCB to embed the chips. This polymer layer is photostructured to open contact pads on the base chips as well as on the embedded chips. The next step is the built-up of metal routing. Here a semi-additive process is used, which means electroplating on a sputter seed layer of TiW/Cu. This metal layer is followed by another polymer layer for passivation and acting as a solder mask. Then Under Bump Metallization (UBM) is applied again by electroplating. Finally Balling is done either by Ball Placement or by Solder Paste Printing. Now the wafer is diced and the full ASIC-MEMS package can be flip chiped onto a Printed Circuit Board (PCB). The technology will be demonstrated by the project RESTLES (Reliable System Level Integration of Stacked Chips on MEMS). RESTLES will integrate technologies like silicon MEMS, ASIC, wafer thinning, chip stacking and flip chip to one pack-aged chip stack at die scale. The influence of the heterogeneous stack on performance and control mechanisms to eliminate parasitic effects will be investigated.

: http://publica.fraunhofer.de/documents/N-125147.html