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3-D Thin Chip Integration Technology - from Technology Development to Application

 
: Fritzsch, T.; Mrossko, R.; Baumgartner, T.; Toepper, M.; Klein, M.; Wolf, J.; Wunderle, B.; Reichl, H.

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Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Conference on 3D System Integration, 3DIC 2009 : San Francisco, California, 28 - 30 September 2009
NEW YORK: IEEE, 2009
ISBN: 978-1-4244-4511-0
ISBN: 978-1-4244-4512-7
pp.138-145
International Conference on 3D Systems Integration (3DIC) <1, 2009, San Francisco/Calif.>
English
Conference Paper
Fraunhofer IZM ()

Abstract
3-D technologies open a wide range of chip integration possibilities for microelectronic systems. Most of these technologies are using Through-Silicon Vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture: The core component of this planar integration technology is the embedding of ultra-thin chips into a multi layer thin film routing on a larger sized substrate chip on wafer level. All process steps are performed with standard back end equipment used for redistribution and other wafer level packaging technologies. Using advanced grinding and etching technologies thinning of CMOS chips is possible down to a thickness of 20 to 40 microns with high yield. These ultra-thin chips can be integrated into BCB-copper multi layer redistribution on wafer level. A test chip with peripheral arranged daisy chains was thinned down to a thickness of 35 mu m. This thin chip was mounted onto a larger substrate chip on wafer level which also contains daisy chain interconnection between the embedded chip and the substrate. A third smaller daisy chain chip was flip chip mounted onto the two chips to result in a three level chip interconnection stack. The technology development was accompanied by electrical characterizations and reliability investigations including temperature cycle test between -55 degrees C and 125 degrees C. Beside this technological investigation a thermo-mechanical model was developed to investigate the stress accumulation during individual process steps as well as thermal cycling steps. The simulation indicates possible regions with a higher material failure risk during life time in accordance with the experimental evaluation and potential for further optimization. In addition to the technology development first examples of application will be given. Using the thin chip integration technology a functional demonstrator for wireless activity monitoring was realized within the e-CUBES project founded by the European Commision. A second functional TCI demonstrator will be realized within the RESTLES project, founded by the German government. This demonstrator is focused on the conditions in the automotive industry.

: http://publica.fraunhofer.de/documents/N-125094.html