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2,5-Dimensional System-In-Package Integration - Technology Oriented Parameter Model For Physical Design

 
: Polityko, D.D.; Guttowski, S.; Reichl, H.

Reichl, H. ; Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration -IZM-, Berlin:
Micro System Technologies 2005 : Micro Electro, Opto, Mechanical Systems & Components International Conference & Exhibition, October 5-6, 2005, Munich, Germany
Poing: Franzis, 2005
ISBN: 3-7723-7040-3
pp.500-507
International Conference on Micro Electro, Opto, Mechanical Systems & Components <2005, München>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Compared to the monolithic integration System-on-Chip, System-In-Package (SiP) allows e.g. an easier integration of very heterogeneous components. Nevertheless, there are a number of advantages in contrast to the 2D solutions (signal paths, size/weight, etc). Whilst a PCB/MCM designer has several clear criteria to make a decision regarding substrate and interconnection technology (wiring density, number of layer, pad pitch), there is no clearly defined criteria for choosing optimal vertical SiP technique. The designer is faced with many different technological solutions (e.g. stacked wire bonded dies, circuitry on folded flex, soldered flipchip modules). The derivation of a practical parameter table from different technologies would simplify the geometry/technological decisions and also allow for SiP design tools.

Within the 2,5D integration (vertically integrated layers) the physical design (PD) could be subdivided into two stages:
1. Global Layout, which can be abstracted away from any certain technology,
2. Detailed Layout/implementation, which is obviously based on definite technology.

In analogy to PCB/MCM- and IC-design, both stages consist of three main steps: Partitioning, Placement and Routing.
In the beginning of the PD, the net list and the component set are for the most part defined. The aim of global partitioning is to group the components and to allocate them on certain vertical layers. Global placement means the arrangement of layers in stack, and global routing is in this case the optimization of the electrical wiring/nets between the layers. These steps can be formulated as a mathematical problem with a number of objectives, such as e.g. floorplan/volume minimization for partitioning. Before starting the detailed layout, the technology for the stacking and vertical interconnection MUST be selected. The rare publications on the PD for 2,5D are targeting only one specific SiP technology. The contribution of presented work is the investigation of objective basics for this selection. There are no standardizations for vertical integrated SiPs. Based on primarily technological criteria, the classifications of 2,5D technologies by "Interconnects Technology" (Area, Periphery) or by "Integration Level" (Wafer-, Chip-, Module-Stack) have been presented. The abstract consideration of "technology-free" physical and electrical attributes results in other classification, which is more helpful for design purposes. The SiP as "System" aims not only at transferring all the components terminals outside the package. Thus there are connected/redistributed nets.

Classification of four main technology groups in accordance to "Redistribution Level" is presented as follows:
1. No redistribution in vertical wiring possible (in this case it can be called vertical interconnect VIC), lower redistribution level in lateral wiring (represented mostly by wire bonded die stakes, e.g. Sharp),
2. No redistribution in VICs and high redistribution level in lateral wiring (solutions with functional layer on stacked modules, e.g. North),
3. Redistribution level in vertical and lateral wiring is approximately equal (solutions with components on the folded flexible substrate,e.g. Tessera),
4. Medium and approximately equal redistribution level in vertical und lateral wiring, (stacked and molded devices with connecting metallization on the sidewalls, 3D Plus, Irvine).

Considering the net complexity schema and being supported by essential parameters (partly presented in Fig.1), a SiP designer can choose between four technology groups and start detailed layout targeting the chosen technology. Proposed parameters set is currently under development. Their interaction offers interesting objectives for investigations, e.g. dependence of VIC-Pitch and -Density on the Layer Gap (Fig.2: case study results for soldered modules). Further studies should embrace earlier system costs and size estimations, implementation of electrical and thermal simulation models.

: http://publica.fraunhofer.de/documents/N-120429.html