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Forced Convection Interlay Cooling in Vertically Integrated Packages

: Brunschwiler, T.; Michel, B.; Rothuizen, H.; Kloter, U.; Wunderle, B.; Oppermann, H.; Reichl, H.


IEEE Computer Society:
11th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, I-THERM
ISBN: 978-1-4244-1701-8
ISSN: 1087-9870
Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems (ITHERM) <11, 2008, Orlando>
Conference Paper
Fraunhofer IZM ()

The heat removal capability of area-interconnect-compatible interlayer cooling in vertically integrated, high-performance chip stacks was characterized with de-ionized water as coolant. Correlation-based predictions and computational fluid dynamic modeling of cross-flow heat-removal structures show that the coolant temperature increase due to sensible heat absorption limits the cooling performance at hydraulic diameters <= 200 µm. An experimental investigation with uniform and double-side heat flux at Reynolds numbers <= 1000 and heat transfer areas of 1 cm2 was carried out to identify the most efficient interlayer heat-removal structure. Parallel plate, microchannel, pin fin, and their combinations with pins using in-line and staggered configurations with round and drop-like shapes at pitches ranging from 50 to 200 µm and fluid structure heights of 100 to 200 µm were tested. A hydrodynamic flow regime transition responsible for a local junction temperature minimum was observed for pin fin inline structures. The experimental data was extrapolated to predict maximal heat flux in chip stacks with a 4-cm2 heat transfer area. The performance of interlayer cooling strongly depends on this parameter, and drops from > 200 W/cm2 at 1 cm2 and > 50 µm interconnect pitch to < 100 W/cm2 at 4 cm2.