Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

System Integration on Wafer Level - Requirements and Technical Solutions

: Wolf, M.J.; Michel, B.; Ramm, P.; Reichl, H.

Micromaterials and nanomaterials 7 (2007), pp.272-273
ISSN: 1619-2486
International Congress on Microreliability and Nanoreliability in Key Technology Applications (MNR) <1, 2007, Berlin>
Conference Paper
Fraunhofer IZM ()

System integration technologies have increasingly become a strategic enabler for the entire economy and an important factor for suppliers and users of electronic products. Faced with the rapid development of the IC technology the traditional packaging is changing into a complex system integration technique to satisfy the growing demand in terms of increased functionality, performance and miniaturization. Electronic systems are used in broad application areas such as e.g., information & communication, computing, automotive and consumer. New applications are arising in the field of health monitoring, security, etc.. The functionality of future systems can be considerably enlarged by the integration of mechanical, optical and biological functions. This requires the integration of electrical and non-electrical (sensor-, actuator-) functions. These so called Hetero Systems have to create adequate interfaces for the different application scenarios. The realization of Hetero Systems requires new architectures, new components and new system integration technologies as well. Therefore the progresses in nano- and microelectronics, microsystem technologies, bioelectronics and photonics are important factors. Hetero System Integration will be able to combine devices and components originating from different technologies for sensing, electrical signal and data processing, wireless communication, power conversion and storage. The Hetero System Integration concept is also particularly gaining importance due to the shorter time to market cycle and a high degree of flexibility at lower cost and risk assessment.

The ITRS roadmap as well as technical roadmaps from other organizations (e.g. iNEMI, Jisso, Jeita) predict the increasing importance of System in Package (SiP) and 3D integration technologies on different levels. The ability to integrate further electronic devices on silicon wafers is a decisive criterion for further development of wafer level packaging technologies (WLP). Examples are the integration of passive components (resistors, capacitors, inductors, etc.) and embedding of active devices.

Advanced electronic systems, e.g. 3D image processors and systems with integrated sensors, processors, ASIC´s, memories, radio interface (e.g. e Grain), are driven by performance enhancement and miniaturization. Three-dimensional integration technologies will be used to overcome the performance bottleneck which result from the predicted ?fundamental wiring crisis? caused by signal propagation delay.
The "highly minaturized sonsor nodes" of Fraunhofer IZM "eGrain concept" attempts to link all types of system integration techniques and represents a full value chain from microelectronics and microsystems. These tiny atonomous sensor nodes require the integration of devices from different technologies e.g. MEMS sensors, radio interface, DSP and power sources. The relaization of these ultra-miniaturized self-sufficient wireless sensor nodes requires heterogeneous technologies on different levels including e.g. advanced assembly and interconnection technoloogies, integration of passive devices, thin circuit device and sensor integration, flexible functional substrate and 3D vertical integration at wafer level. The presentation will discuss Wafer Level System integration Approaches with focus on vertical system integration (VSI), which is characterized by very high dense vertical inter-chip wiring with freeliy positioned through-Si vias (TSV). The corresponding fabrication is based on via-formationand metallization, thinning and adjusted bonding of completely processed device wafers. The so-called ICV-SLID concept is based on the bonding of top chips to a bottom wafer by very thin soldering layers (e.g. Cu/Sn). Alternative micro-bumps (e.g. SnAg) are used as well. The required underbump metallization (UBM) has to be chosen with respect to the intermetallic compound (IMC) formation. The through-Si vias are fully processed - etched and metallised - prior to the thinning sequence, with the advantage that the later stacking of the separate known good dice to the bottom device wafer is the final step of the 3D integration process flow. As a fully modular concept, the VSI approach allows the formation of multiple device stacks with a very high via interconnect density .