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Technology Requirements for Chip-On-Chip Packaging Solution

: Töpper, M.; Fritzsch, T.; Glaw, V.; Jordan, R.; Lopper, C.; Röder, J.; Dietrich, L.; Lutz, M.; Oppermann, H.; Ehrmann, O.; Reichl, H.

ECTC 2005, the 55th Electronic Components and Technology Conference. Proceedings. CD-ROM : Lake Buena Vista, Florida; May 31-June 3
New York, NY: IEEE, 2005
ISBN: 0-7803-8907-7
Electronic Components and Technology Conference (ECTC) <55, 2005, Lake Buena Vista/Fla..>
Conference Paper
Fraunhofer IZM ()

The trend towards smaller, lighter and thinner products requires a steady miniaturization which has brought-up the
concept of Chip Scale Packaging (CSP). The next step to reduce packaging cost was the chip packaging directly on the
wafer. Wafer Level Packaging (WLP) enables the FC assembly on PWB without interposers. New and improved
microelectronic systems require significant more complex devices which could limit the performance due to the wiring
of the subsystems on the board. 3-D packaging using the existing WLP infrastructure is one of the most promising
approaches. Stacking of chips for chip-on-chip packages can be done by wafer-to-wafer stacking or by chip-to-wafer
stacking which is preferable for yield and die size considerations. This chip-on-chip packaging requires a base
die with redistribution traces to match the I/O layout of both dice. This allows the combination of the performance
advantage of flip chip with the options of WLP. To avoid the flip chip bonding process the thin chip integration (TCI)
concept can be used. Key elements of this approach are extremely thin ICs which are incorporated into the redistribution. This technology offers excellent electrical properties of the whole microelectronic system. The focus of this paper will be the technology requirements for the realization of different kinds of chip-onchip packages.