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Technical understanding of resin-coated-copper (RCC) lamination processes for realization of reliable chip embedding technologies

: Manessis, D.; Yen, S.F.; Ostmann, A.; Aschenbrenner, R.; Reichl, H.


Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 57th Electronic Components and Technology Conference 2007. Vol.1 : Sparks, NV, 29 May - June 1, 2007
Piscataway, NJ: IEEE, 2007
ISBN: 1-4244-0984-5
ISBN: 1-4244-0985-3
Electronic Components and Technology Conference (ECTC) <57, 2007, Reno/Nev.>
Conference Paper
Fraunhofer IZM ()

This paper focuses on the lamination technology employed for the development of a production-capable technology for embedding active components and chips into printed circuit boards (PCBs). The work is jointly performed by a consortium of partners from industry and research within the frame of the European research project "Hiding Dies". It turns out that if lamination principles from the conventional PCB manufacturing can be well tuned and controlled then chip embedding can be achieved by economic means. In specific, Resin-Coated-Copper (RCC) films can be laminated on assembled chips and components providing the polymer dielectric matrix for further 3D package processing. Lamination of RCC films can superbly replace the spin-coating processes. The chips are attached using adhesive pastes or adhesive films on multilayer FR4 boards. Precise thickness control of the adhesive is essential for maintaining uniform thicknesses of the build-up dielectric on top of the chip. Filled and no-filled epoxy RCC's have been successfully used to laminate very thin (~50mum) as well as relatively thick chips up to 200mum. The lamination pressure profile should be very carefully adjusted to avoid chip breakage upon lamination especially for the very thin chips. Pressures from 5 up to 20 bars and heating rates of 3degC/min and 8degC/min have been used to study the integrity of the resultant interfaces. Laminated samples were exposed to Thermal Cycling from -55degC to 125degC for 1000 cycles and to Jedec level 1 and 3 tests. Shear testing was also employed as evaluation tool for interface strength. From interface morphology and flatness standpoint, RCC's and the die attach materials provide flatness, parallelism and a desirable 20-30mum epoxy thickness above the chip for optimum via laser drilling to chip pads in chip-in-polymer process. After 1000 thermal cycles, there are no signs of interface delaminations. However, after JEDEC level 1, interface delamination occurs at the interfac- es of RCC-Cu/epoxy, epoxy/chip and chip/die attach material. Lamination at the highest heating rate and pressures of 5 and 10 bar yields interfaces with many voids and a thick epoxy thickness above chip compared to other lamination conditions. Based on shear test results with a shear speed of 100mum/sec and shear height of 40mum, the low pressures of 5 bar and 10 bar and the highest heating rate result in lower shear strength values than the slowest heating rate of 3 degC/min. Lamination at a pressure of 20 bar yields embedded structures with the highest strength regardless the lamination heating rate chosen. These results strongly indicate significance of lamination pressure for good adhesion at epoxy/chip and epoxy/substrate interfaces. Lamination of a combination of 2-prepreg layers and RCCs with 25 mum epoxy thickness can achieve embedding of chips with even 200mum thickness. Reliability testing of the laminated embedded chips have shown very promising results. Lamination related issues are discussed and lamination process tips are provided for successful chip embedding and further 3D package processing.