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Resistance analysis of wrapped through emitters

 
: Mingirulli, N.; Driessen, M.; Grote, D.; Biro, D.; Preu, R.

:
Fulltext urn:nbn:de:0011-n-1187853 (175 KByte PDF)
MD5 Fingerprint: c97f3d586ff3d8ae2fe3f7386d985496
© 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Created on: 17.11.2012


IEEE Electron Devices Society:
33rd IEEE Photovolatic Specialists Conference, PVSC 2008. Proceedings. Vol.1 : San Diego, CA, May 11 - 16, 2008
Piscataway, NJ: IEEE, 2008
ISBN: 978-1-4244-1640-0
ISBN: 1-4244-1640-X
ISBN: 978-1-4244-1641-7
pp.445-448
Photovoltaic Specialists Conference (PVSC) <33, 2008, San Diego/Calif.>
English
Conference Paper, Electronic Publication
Fraunhofer ISE ()

Abstract
To analyze the via-hole emitter resistance two different test devices were designed consisting of symmetric n(+)pn(+)-structures whereas the emitter via-holes are ideally the only connection between the two emitter layers. The first device allows measuring the resistance of a single via hole. The second device features a plurality of via holes, in order to determine the resistance of 25...100 via-holes in parallel. Subtracting spreading resistance and geometry contributions with an analytical approach the via-hole resistance can be deduced from both methods. The presented approach reveals the series resistance contribution of the emitter via-hole independently of the complete solar cell device. Further it permits to test a variety of emitter formation processes, metallization schemes and damage etching or texturization steps regarding their specific series resistance contribution or the general feasibility of a process sequence respectively.

: http://publica.fraunhofer.de/documents/N-118785.html