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Investigation of solder bumps, flip chip assembly, reliability and passive alignment using Au/Sn

: Hutter, M.; Klein, M.; Engelmann, G.; Oppermann, H.

Michel, B.; Aschenbrenner, R.:
The world of electronic packaging and system integration : Anniversary edition 60th birthday of Herbert Reichl
Dresden: ddp Goldenbogen, 2004
ISBN: 3-932434-76-5
ISBN: 978-3-932434-76-1
Book Article
Fraunhofer IZM ()

Flip chip assembly experiments using small electroplated Au/Sn bumps, i.e. bumps of 50 µm in diameter and less, are carried out. After plating the bumps consist of a Au layer with a thinner Sn layer on top. Normally a reflow process follows. However, the experiments prove that due to geometrical reasons as plated bumps rather than reflowed ones shall be used for bump sizes below 50 µm in diameter in order to achieve a high yield flip chip assembly process. Furthermore thermal cycling tests were carried out using flip chip assemblies consisting of a GaAs die soldered to a BCB thin film Silicon substrate. Most recent results reveal that beside utilizing the self-alignment effect a promising approach to achieve high precision alignment passively is to use micro¬mechanical stops.