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250 MBit/s 64-state soft-decision Viterbi decoder on a cell CPU

: Wieruch, D.; Kühling, D.; Ibing, A.

Balog, P. ; Institute of Electrical and Electronics Engineers -IEEE-, Austria Section:
Tagungsband zur Informationstagung Mikroelektronik 08 : Wien, 15. - 16. Oktober 2008
Wien: OVE, 2008 (Schriftenreihe OVE 50)
ISBN: 978-3-85133-049-6
Informationstagung Mikroelektronik (ME-Tagung) <2008, Wien>
Conference Paper
Fraunhofer HHI ()
CPU (Zentraleinheit); Decodierer; feldprogrammierbare-Gate-Array-Schaltung; Programmfehlerkorrektur; Algorithmus

A 64-state soft-decision Viterbi algorithm implementation on a Cell CPU running at 2.8 GHz is presented, which achieves a throughput of 250 MBit/s, 500 MBit/s encoded data, where the 8 SPU cores process different packets in parallel. Evaluations are done using the IEEE 802.11a, WiMAX and DVB code polynomials. The implementation is done in C language using the GNU C compiler. The code uses optimizations like instruction level parallelism, loop unrolling and indepent processor pipelines.