• English
  • Deutsch
  • Log In
    Password Login
    Research Outputs
    Fundings & Projects
    Researchers
    Institutes
    Statistics
Repository logo
Fraunhofer-Gesellschaft
  1. Home
  2. Fraunhofer-Gesellschaft
  3. Konferenzschrift
  4. A multi-level modeling approach rendering virtual test engineering (VTE) economically viable for highly complex telecom circuits
 
  • Details
  • Full
Options
1999
Conference Paper
Title

A multi-level modeling approach rendering virtual test engineering (VTE) economically viable for highly complex telecom circuits

Abstract
Virtual Test Engineering is a very promising IC test technique to meet time-to-market needs: All constituents for production test (testprogram, loadboard) can be debugged before 1st silicon. However, the cost for modeling and simulation can become prohibitive if not minimized by a multi-level approach. A VTE experiment was performed for a telecom IC proving that the modeling effort can be kept below 1 month, with the simulation time better than 2 min. per ms real test time.
Author(s)
Einwich, K.
Krampl, G.
Hoppenstock, R.
Koutsandreas, P.
Sattler, S.
Mainwork
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings  
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE) 1999  
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Keyword(s)
  • communication

  • Cookie settings
  • Imprint
  • Privacy policy
  • Api
  • Contact
© 2024