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A multi-level modeling approach rendering virtual test engineering (VTE) economically viable for highly complex telecom circuits

: Einwich, K.; Krampl, G.; Hoppenstock, R.; Koutsandreas, P.; Sattler, S.

European Design Automation Association -EDAA-; IEEE Computer Society; Association for Computing Machinery -ACM-, Special Interest Group on Design Automation -SIGDA-:
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings : Munich, Germany, March 9 - 12, 1999
Los Alamitos, Calif.: IEEE Computer Society, 1999
ISBN: 0-7695-0078-1
ISBN: 0-7695-0079-X
ISBN: 0-7695-0080-3
Design, Automation and Test in Europe Conference and Exhibition (DATE) <1999, München>
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Virtual Test Engineering is a very promising IC test technique to meet time-to-market needs: All constituents for production test (testprogram, loadboard) can be debugged before 1st silicon. However, the cost for modeling and simulation can become prohibitive if not minimized by a multi-level approach. A VTE experiment was performed for a telecom IC proving that the modeling effort can be kept below 1 month, with the simulation time better than 2 min. per ms real test time.