A multi-level modeling approach rendering virtual test engineering (VTE) economically viable for highly complex telecom circuits

Virtual Test Engineering is a very promising IC test technique to meet time-to-market needs: All constituents for production test (testprogram, loadboard) can be debugged before 1st silicon. However, the cost for modeling and simulation can become prohibitive if not minimized by a multi-level approach. A VTE experiment was performed for a telecom IC proving that the modeling effort can be kept below 1 month, with the simulation time better than 2 min. per ms real test time.