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| 2011 | TSV based silicon interposer technology for wafer level fabrication of 3D SiP modules
Zoschke, K.; Wolf, J.; Lopper, C.; Kuna, I.; Jurgensen, N.; Glaw, V.; Samulewicz, K.; Roder, J.; Wilke, M.; Wunsch, O.; Klein, M.; Suchodoletz, M.V.; Oppermann, H.; Braun, T.; Wieland, R.; Ehrmann, O. | Conference Paper |
| 2010 | 3D-integration of silicon devices: A key technology for sophisticated products
Klumpp, A.; Ramm, P.; Wieland, R. | Conference Paper |
| 2010 | Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC
Andricek, L.; Beimforde, M.; Klumpp, A.; Macchiolo, A.; Merkel, K.-R.; Moser, H.-G.; Nisius, R.; Richter, R.H.; Weber, J.; Weigell, P.; Wieland, R. | Conference Paper |
| 2010 | Silicon interposer for heterogeneous integration
Wolf, M.J.; Zoschke, K.; Wieland, R.; Klein, M.; Lang, K.-D.; Reichl, H. | Conference Paper |
| 2010 | Silicon-interposer with high density Cu-filled TSVs
Wieland, R.; Zoschke, K.; Jürgensen, N.; Merkel, R.; Nebrich, L.; Wolf, J. | Conference Paper |
| 2009 | 3D image sensor SiP with TSV silicon interposer
Limansyah, I.; Wolf, J.; Klumpp, A.; Zoschke, K.; Wieland, R.; Klein, M.; Oppermann, H.; Nebrich, L.; Heinig, A.; Pechlaner, A.; Reichl, H.; Weber, W. | Conference Paper |
| 2009 | 3D integration of image sensor SiP using TSV silicon interposer
Wolf, M.J.; Zoschke, K.; Klumpp, A.; Wieland, R.; Klein, M.; Nebrich, L.; Heinig, A.; Limansyah, I.; Weber, W.; Ehrmann, O.; Reichl, H. | Conference Paper |
| 2009 | 3D process integration - requirements and challenges
Wolf, M.J.; Klumpp, A.; Zoschke, K.; Wieland, R.; Nebrich, L.; Klein, M.; Oppermann, H.; Ramm, P.; Ehrmann, O.; Reichl, H. | Conference Paper |
| 2009 | Electrostatic carrier technique for thin wafer processing
Landesberger, C.; Wieland, R.; Ramm, P.; Bock, K. | Journal Article |
| 2009 | Electrostatic wafer handling for thin wafer processing
Landesberger, C.; Wieland, R.; Klumpp, A.; Ramm, P.; Drost, A.; Schaber, U.; Bonfert, D.; Bock, K. | Conference Paper |
| 2009 | Etch performance of Ar/N2/F2 for CVD/ALD chamber clean
Riva, M.; Pittroff, M.; Schware, T.; Oshinowo, J.; Wieland, R. | Journal Article |
| 2009 | Superior etch performance of Ar/N2/F2 for PECVD chamber clean
Riva, M.; Pittroff, M.; Schwarze, T.; Fluor, S.; Wieland, R.; Oshinowo, J. | Conference Paper |
| 2008 | Keep your chamber clean
Riva, M.; Pittroff, M.; Schwarze, T.; Oshinowo, J.; Wieland, R. | Journal Article |
| 2008 | Metallization by chemical vapor deposition of W and Cu
Klumpp, A.; Wieland, R.; Ecke, R.; Schulz, S.E. | Book Article |
| 2008 | Through silicon via technology - processes and reliability for wafer-level 3D system integration
Ramm, P.; Wolf, M.J.; Klumpp, A.; Wieland, R.; Wunderle, B.; Michel, B.; Reichl, H. | Conference Paper |
| 2008 | Verfahren zum Herstellen einer halbleiterbasierten Schaltung und halbleiterbasierte Schaltung mit dreidimensionaler Schaltungstopologie
Reichl, H.; Wolf, J.; Wieland, R.; Zoschke, K. | Patent |
| 2007 | 3D system integration
Klumpp, A.; Merkel, R.; Ramm, P.; Wieland, R. | Conference Paper |
| 2007 | 3D-integrated Si- and SiGe CMOS-devices by ICV-SLID technology
Wieland, R.; Ecke, R.; Klumpp, A.; Merkel, R.; Schulz, S.E.; Ramm, P. | Conference Paper |
| 2007 | Bipolarer Traegerwafer und mobile, bipolare, elektrostatische Waferanordnung
Wieland, R.; Bollmann, D. | Patent |
| 2006 | Mobile, unipolare, elektrostatische Waferanordnung
Bollmann, D.; Bleier, M.; Wieland, R. | Patent |
| 2005 | 3D integration of CMOS transistors with ICV-SLID technology
Wieland, R.; Bonfert, D.; Klumpp, A.; Merkel, R.; Nebrich, L.; Weber, J.; Ramm, P. | Conference Paper, Journal Article |
| 2005 | Betriebsfeste Auslegung hochbelasteter Kunststoffbauteile im Motorraum
Gumnior, P.; Gerharz, J.; Moosbrugger, E.; Wieland, R. | Journal Article |
| 2005 | Betriebsfeste Auslegung hochbelasteter Kunststoffbauteile im Motorraum
Gumnior, P.; Gerharz, J.; Moosburger, E.; Wieland, R. | Journal Article |
| 2005 | High quality strained Si/SiGe substrates for CMOS and optical devices
Weber, J.; Nebrich, L.; Bensch, F.; Neumeier, K.; Vogg, G.; Wieland, R.; Bonfert, D.; Ramm, P. | Conference Paper |
| 2005 | Process integration of infrared-sensitive PIN photodiodes and CMOS transistors in a single-SiGe substrate
Nebrich, L.; Neumeier, K.; Stadler, A.; Weber, J.; Bensch, F.; Kreuzer, S.; Vogg, G.; Herrmann, K.; Klumpp, A.; Wieland, R.; Bonfert, D.; Soldner, W.; Ramm, P. | Conference Paper, Journal Article |
| 2004 | Betriebsfeste Auslegung hochbelasteter Kunststoffbauteile im Motorrraum
Moosburger, E.; Wieland, R.; Gumnior, P.; Gerharz, J. | Conference Paper |
| 2004 | Handhabungswafer zur Handhabung von Substraten
Wieland, R.; Spoehrle, H. | Patent |
| 2004 | Vertical system integration by using inter-chip vias and solid-liquid interdiffusion bonding
Klumpp, A.; Merkel, R.; Ramm, P.; Weber, J.; Wieland, R. | Journal Article |
| 2004 | Vertical System Integration Technology for High Speed Applications by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding
Klumpp, A.; Merkel, R.; Weber, J.; Wieland, R.; Elst, G.; Ramm, P. | Book Article |
| 2003 | 3D system integration technologies
Ramm, P.; Klumpp, A.; Merkel, R.; Weber, J.; Wieland, R.; Ostmann, A.; Wolf, J. | Conference Paper |
| 2003 | Chip-to-wafer stacking technology for 3D system integration
Klumpp, A.; Merkel, R.; Wieland, R.; Ramm, P. | Conference Paper |
| 2002 | InterChip via technology by using copper for vertical system integration
Ramm, P.; Bonfert, D.; Ecke, R.; Iberl, F.; Klumpp, A.; Riedel, S.; Schulz, S.E.; Wieland, R.; Zacher, M.; Gessner, T. | Conference Paper |
| 2001 | Copper metallization scheme for vertical chip integration
Riedel, S.; Ecke, R.; Schulz, S.E.; Gessner, T.; Wieland, R.; Leutenecker, R.; Klumpp, A.; Ramm, P. | Conference Paper |
| 2001 | Interchip Via Technology for Vertical System Integration
Ramm, P.; Bonfert, D.; Gieser, H.; Haufe, J.; Iberl, F.; Klumpp, A.; Kux, A.; Wieland, R. | Conference Paper |