Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.
2019Identification of Soft Failure Mechanisms Triggered by ESD Stress on a Powered USB 3.0 Interface
Koch, Sebastian; Orr, Benjamin J.; Gossner, H.; Gieser, Horst A.; Maurer, Linus
Journal Article
2019Integrated Flow for Reverse Engineering of Nanoscale Technologies
Lippmann, Bernhard; Werner, Michael; Unverricht, Niklas; Singla, Aayush; Egger, Peter; Dübotzky, Anja; Gieser, Horst; Rasche, Martin; Kellermann, Oliver; Graeb, Helmut
Conference Paper
2019Secondary Discharge during System Level ESD Tests
Wolf, Heinrich; Weber, Johannes; Gieser, Horst
Conference Paper
2019Stress current slew rate sensitivity of an ultra-high-speed interface IC
Weber, Johannes; Fung, Rita; Wong, Richard; Wolf, Heinrich; Gieser, Horst; Maurer, Linus
Journal Article
2017Charge/discharge effects and ESD prevention at the example of RFID smart card manufacturing
Jacob, Peter; Thiemann, Uwe; Weber, Johannes; Gieser, Horst; Wolf, Heinrich
Conference Paper
2017Correlation limits between capacitively coupled transmission line pulsing (CC-TLP) and CDM for a large chip-on-flex assembly
Weber, Johannes; Reinprecht, Wolfgang; Gieser, Horst; Wolf, Heinrich; Maurer, Linus
Conference Paper
2017Correlation study of different CDM testers and CC-TLP
Weber, Johannes; Kaschani, Karim T.; Gieser, Horst; Wolf, Heinrich; Maurer, Linus; Famulok, Nicolai; Moser, Reinhard; Rajagopal, Krishna; Sellmayer, Michael; Sharma, Anmol; Tamm, Heiko
Conference Paper
2017Simulation and experimental investigation of slew rate related ESD failures of CDM and CC-TLP
Weber, Johannes; Kaschani, Karim T.; Gieser, Horst; Wolf, Heinrich; Maurer, Linus; Famulok, Nicolai; Moser, Reinhard; Rajagopal, Krishna; Sellmayer, Michael; Sharma, Anmol; Tamm, Heiko
Conference Paper
2016Mechanical reliability analysis of ultra-thin chip-on-foil assemblies under different types of recurrent bending
Palavesam, N.; Bonfert, D.; Hell, W.; Landesberger, C.; Gieser, H.; Kutter, C.; Bock, K.
Conference Paper
2016Novel processing scheme for embedding and interconnection of ultra-thin IC devices in flexible chip foil packages and recurrent bending reliability analysis
Landesberger, C.; Palavesam, N.; Hell, W.; Drost, A.; Faul, R.; Gieser, H.; Bonfert, D.; Bock, K.; Kutter, C.
Conference Paper
2015Electrical behaviour of Flip-Chip bonded thin silicon chip-on-foil assembly during bending
Palavesam, N.; Bonfert, D.; Hell, W.; Landesberger, C.; Gieser, H.; Kutter, C.; Bock, K.
Conference Paper
2015Electrostatic discharge sensitivity investigation on organic field-effect thin film transistors
Lim, T.; Gieser, H.; Santarelli, L.; Cacialli, F.
Conference Paper
2015ESD performance evaluation of powered high-speed interfaces
Koch, S.; Gossner, H.; Gieser, H.; Maurer, L.
Conference Paper
2015Secondary discharge - a potential risk during system level ESD testing
Wolf, H.; Gieser, H.
Conference Paper
2015Using CC-TLP to get a CDM robustness value
Esmark, K.; Gaertner, R.; Seidl, S.; Nieden, F. zur; Wolf, H.; Gieser, H.
Conference Paper
2014Multifunctional system integration in flexible substrates
Bock, K.; Yacoub-George, E.; Hell, W.; Drost, A.; Wolf, H.; Bollmann, D.; Landesberger, C.; Klink, G.; Gieser, H.; Kutter, C.
Conference Paper
2013Heterointegration technologies for high frequency modules based on film substrates
Bock, K.; Yacoub-George, E.; Wolf, H.; Landesberger, C.; Klink, G.; Gieser, H.
Conference Paper
2013Transmission lines on flexible substrates with minimized dispersion and losses
Wolf, H.; Gieser, H.; Maurer, L.
Conference Paper
2013Transmission lines on flexible substrates with minimized dispersion and losses
Wolf, H.; Gieser, H.; Maurer, L.
Conference Paper
2012ESD risk evaluation of automatic semiconductor process equipment-a new guideline of the german ESD Forum e.V.
Jacob, P.; Gärtner, R.; Gieser, H.; Helling, K.; Pfeifle, R.; Thiemann, U.; Wulfert, F.; Rothkirch, W.
Conference Paper
2011Electrical stress on thin film TaN resistive structures
Bonfert, D.; Gieser, H.; Bock, K.; Svasta, P.; Ionescu, C.
Conference Paper
2010An adapted filament model for accurate modeling of printed coplanar lines with significant surface roughness and proximity effects
Curran, B.; Ndip, I.; Werner, C.; Ruttkowski, V.; Maiwald, M.; Wolf, H.; Zoellmer, V.; Domann, G.; Guttovski, S.; Gieser, H.; Reichl, H.
Journal Article
2010Electrical stress on film resistive structures on flexible substrates
Bonfert, D.; Klink, G.; Gieser, H.; Bock, K.; Svasta, P.; Ionescu, C.
Conference Paper
2010Pulsed stress behavior of platinum thin films
Bonfert, D.; Gieser, H.; Bock, K.; Svasta, P.; Ionescu, C.
Conference Paper
2010Rapid prototyping of electronic modules combining aerosol printing and ink jet printing
Gieser, H.A.; Bonfert, D.; Hengelmann, H.; Wolf, H.; Bock, K.; Zollmer, V.; Werner, C.; Domann, G.; Bahr, J.; Ndip, I.; Curran, B.; Oehler, F.; Milosiu, H.
Conference Paper
2009Capacitive coupled TLP (CC-TLP) and the correlation with the CDM
Wolf, H.; Gieser, H.; Bock, K.; Duvvury, C.; Jahanzeb, A.; Lin, Y.-Y.
Conference Paper
2009Investigating the CDM susceptibility of IC's at package and wafer level by capacitive coupled TLP
Wolf, H.; Gieser, H.; Walter, D.
Journal Article
2009Investigating the ESD robustness of RF circuits and elements by transmission line pulsing
Wolf, H.; Gieser, H.; Bock, K.
Conference Paper
2009Modeling and Measurement of Coplanar Transmission Lines with Significant Proximity and Surface Roughness Effects
Curran, B.; Ndip, I.; Werner, C.; Ruttkowski, V.; Maiwald, M.; Wolf, H.; Zoellmer, V.; Domann, G.; Guttovski, S.; Gieser, H.; Reichl, H.
Conference Paper
2009Pulsed behavior of polymer protection devices
Bonfert, D.; Gieser, H.; Bock, K.; Svasta, P.; Ionescu, C.
Conference Paper
2008Pulsed stress behavior of flexible thick film resistors
Bonfert, D.; Wolf, H.; Gieser, H.; Klink, G.; Bock, K.; Svasta, P.; Ionescu, C.
Conference Paper
2008Transient latch-up analysis of power control device with combined light emission and backside transient interferometric mapping methods
Heer, M.; Pogany, D.; Street, M.; Smith, I.; Riedlberger, F.; Bonfert, D.; Gieser, H.A.
Conference Paper
2008VF-TLP round robin study, analysis and results
Muhonen, K.; Ashton, R.; Barth, J.; Chaine, M.; Gieser, H.; Grund, E.; Henry, L.G.; Meuse, T.; Peachey, N.; Prass, T.; Stadler, W.; Voldman, S.H.
Conference Paper
2007High Current Pulse Stress on Flexible Thick Film Resistors
Bonfert, D.; Wolf, H.; Gieser, H.; Klink, G.; Hemmetzberger, D.
Conference Paper
2007Investigating the CDM susceptibility of ICs at package and wafer level by capacitive coupled TLP
Wolf, H.; Gieser, H.; Walter, D.
Conference Paper
2007Investigations with the capacitive coupled TLP on package and wafer-level
Wolf, H.; Gieser, H.
Conference Paper
2007Survey on very fast TLP and ultra fast repetitive pulsing for characterization in the CDM-domain
Gieser, H.A.; Wolf, H.
Conference Paper
2007Transmission line pulse stress on thick film resistors
Bonfert, D.; Wolf, H.; Gieser, H.; Svasta, P.; Romanescu, A.; Cazacu, E.
Conference Paper
2007Transmission line pulsing behavior of thin film resistors
Bonfert, D.; Wolf, H.; Gieser, H.; Klink, G.; Svasta, P.
Conference Paper
2006ESD susceptibility of submicron air gaps
Wolf, H.; Gieser, H.; Bonfert, D.; Hauser, M.
Conference Paper, Journal Article
2006ESD susceptibility of thick film chip resistors by means of transmission line pulsing
Bonfert, D.; Wolf, H.; Gieser, H.; Stocker, A.
Conference Paper
2006HBM tester parasitic effects on high pin count devices with multiple power and ground pins
Chaine, M.; Meuse, T.; Ashton, R.; Henry, L.G.; Natarajan, M.I.; Barth, J.; Ting, L.; Gieser, H.; Voldman, S.; Farris, M.; Grund, E.; Ward, S.; Kelly, M.; Gross, V.; Narayan, R.; Johnson, L.; Gaertner, R.; Peachey, N.
Conference Paper
2006Transient analysis of ESD protection elements by time domain transmission using repetitive pulses
Wolf, H.; Gieser, H.; Stadler, W.; Wilkening, W.; Rose, P.; Qu, N.
Conference Paper
2006Transient-induced latch-up test setup for wafer-level and package-level
Bonfert, D.; Gieser, H.; Wolf, H.; Frank, M.; Konrad, A.; Schulz, J.
Conference Paper, Journal Article
2005Capacitively coupled transmission line pulsing cc-TLP - a traceable and reproducible stress method in the CDM-domain
Wolf, H.; Gieser, H.; Stadler, W.; Wilkening, W.
Journal Article
2005Comparing arc-free capacitive coupled transmission line pulsing CC-TLP with standard CDM testing and CDM field failures
Gieser, H.; Wolf, H.; Iberl, F.
Conference Paper
2005A dedicated TLP set-up to investigate the ESD robustness of RF elements and circuits
Wolf, H.; Gieser, H.; Soldner, W.; Goßner, H.
Conference Paper, Journal Article
2005Test circuits for fast and reliable assessment of CDM robustness of I/O stages
Stadler, W.; Esmark, K.; Reynders, K.; Zubeidat, M.; Graf, M.; Wilkening, W.; Willemen, J.; Qu, N.; Mettler, S.; Etherton, M.; Nuernbergk, D.; Wolf, H.; Gieser, H.; Soppa, W.; Heyn, V. de; Natarajan, M.; Groeseneken, G.; Morena, E.; Stella, R.; Andreini, A.; Litzenberger, M.; Pogany, D.; Gornik, E.; Foss, C.; Konrad, A.; Frank, M.
Journal Article
2005Transient latch-up: Experimental analysis and device simulation
Bargstädt-Franke, S.; Stadler, W.; Esmark, K.; Streibl, M.; Domanski, K.; Gieser, H.; Wolf, H.; Bala, W.
Journal Article
2004Capacitively Coupled Transmission Line Pulsing CC-TLP - A Traceable and Reproducible Stress Method in the CDM-Domain
Wolf, H.; Gieser, H.; Stadler, W.; Wilkening, W.
Journal Article
2004Characterization and modeling of transient device behavior under CDM ESD stress
Willemen, J.; Andreini, A.; Heyn, V. de; Esmark, K.; Etherton, M.; Gieser, H.; Groeseneken, G.; Mettler, S.; Morena, E.; Qu, N.; Soppa, W.; Stadler, W.; Stella, R.; Wilkening, W.; Wolf, H.; Zullino, L.
Conference Paper, Journal Article
2004Internal behavior of BCD ESD protection devices under TLP and very-fast TLP stress
Blaho, M.; Zullino, L.; Wolf, H.; Stella, R.; Andreini, A.; Gieser, H.A.; Pogany, D.; Gornik, E.
Journal Article
2004Study of CDM Specific Effects for a Smart Power Input Protection Structure
Etherton, M.; Qu, N.; Willemen, J.; Wilkening, W.; Mettler, S.; Dissegna, M.; Stella, R.; Zullino, L.; Andreini, A.; Gieser, H.; Wolf, H.; Fichtner, W.
Conference Paper
2004A Traceable Method for the Arc-free Characterization and Modeling of CDM testers and Pulse Metrology Chains
Gieser, H.A.; Wolf, H.; Soldner, W.; Reichl, H.; Andreini, Antonio; Natarajan, Mahadeva Iyer; Stadler, Wolfgang
Conference Paper
2003Electrical characterisation of a power SO-package in the context of electrostatic discharge
Dörr, I.; Gieser, H.A.; Sommer, G.; Wolf, H.; Wilkening, W.; Willemen, J.; Andreini, A.; Salhi, F.; Fotheringham, G.; John, W.; Reichl, H.
Conference Paper
2003Investigation of ESD protection elements under high current stress in CDM-like time domain using backside laser interferometry
Bychikhin, S.; Dubec, V.; Litzenberger, M.; Pogany, D.; Gornik, E.; Groos, G.; Esmark, K.; Stecher, M.; Stadler, W.; Gieser, H.; Wolf, H.
Conference Paper, Journal Article
2003On-chip electrostatic discharge ESD
Gieser, H.A.
Journal Article
2003Test Circuits for Fast and Reliable Assessment of CDM Robustness of I/O stages
Stadler, W.; Esmark, K.; Reynders, K.; Zubeidat, M.; Graf, M.; Wilkening, W.; Willemen, J.; Qu, N.; Mettler, S.; Etherton, M.; Nuernbergk, D.; Wolf, H.; Gieser, H.; Soppa, W.; Heyn, M. de; Natarajan, M.I.; Groeseneken, G.; Morena, E.; Stella, R.; Andreini, A.; Litzenberger, M.; Pogany, D.; Gornik, E.; Foss, C.; Konrad, A.; Frank, M.
Conference Paper
2003A traceable method for the arc-free characterization and modeling of CDM-testers and pulse metrology chains
Gieser, H.; Wolf, H.; Soldner, W.; Reichl, H.; Andreini, A.; Natarajan, M.I.; Stadler, W.
Conference Paper
2002ESD circuit simulation for the prevention of ESD failures. Application to products in a 0.18 µm CMOS technology
Wolf, H.; Gieser, H.; Stadler, W.; Esmark, K.
Conference Paper
2002ESD in silicon integrated circuits
Anderson, W.; Gieser, H.; Ramaswamy, S.
: Amerasekera, E.A.; Duvvury, C.
Book
2002VERFAHREN UND VORRICHTUNG ZUR GEPULSTEN HOCHSTROMBELASTUNG INTEGRIERTER SCHALTUNGEN UND STRUKTUREN
Gieser, H.
Patent
2001Interchip Via Technology for Vertical System Integration
Ramm, P.; Bonfert, D.; Gieser, H.; Haufe, J.; Iberl, F.; Klumpp, A.; Kux, A.; Wieland, R.
Conference Paper
2000Analyzing the switching behavior of ESD-protection transistors by very fast transmission line pulsing
Wolf, H.; Gieser, H.; Wilkening, W.
Journal Article
2000Vertikal integrierte Schaltung und Verfahren zum Herstellen einer vertikal integrierten Schaltung
Ramm, P.; Gieser, H.
Patent
1999Analyzing the switching behavior of ESD-Protection transistors by very fast transmission line pulsing
Wolf, H.; Gieser, H.; Wilkening, W.
Conference Paper
1999Bipolar model extension for MOS transistors considering gate coupling effects in the HBM ESD domain
Wolf, H.; Gieser, H.; Stadler, W.
Journal Article
1999Characterization and optimization of a bipolar ESD-device by measurements and simulations
Stricker, A.D.; Mettler, S.; Wolf, H.; Mergens, M.; Wilkening, W.; Gieser, H.; Fichtner, W.
Journal Article
1999Investigation into socketed CDM (SDM) tester parasitics
Chaine, M.; Verhaege, K.; Avery, L.; Kelly, M.; Gieser, H.; Bock, K.; Henry, L.G.; Meuse, T.; Brodbeck, T.; Barth, J.
Journal Article
1999Process and equipment simulation of copper CVD using Cu(hfac)vtms
Wolf, H.; Gieser, H.; Riedel, S.; Streiter, R.; Gessner, T.
Journal Article
1999Transient induced latch-up triggered by very fast pulses
Bonfert, D.; Gieser, H.
Conference Paper, Journal Article
1999Transient-Induced Latch-Up Triggered by Very Fast Pulses
Bonfert, D.; Gieser, H.
Journal Article, Conference Paper
1996ESD monitor circuit. A tool to investigate the susceptibility and failure mechanisms of the charged device model
Egger, P.; Gieser, H.; Kropf, R.; Guggenmos, X.
Journal Article
1995Aufbau eines Rechteckimpuls-Generators nach dem Transmission-Line-Prinzip mit verschiedenen Pulsdauern und Belastung von Halbleiter-Schutzstrukturen
Mußhoff, C.; Wolf, H.; Gieser, H.
Conference Paper
1995CDM-Testervergleich anhand eines Monitor-Schaltkreises
Egger, P.; Kropf, R.; Gieser, H.; Guggenmos, X.
Conference Paper
1995ESD monitor circuit. A tool to investigate the susceptibility and failure mechanisms of the charged device model
Egger, P.; Gieser, H.; Kropf, R.; Guggenmos, X.
Conference Paper
1994Analysis of HBM ESD testers and specifications using a fourth-order lumped element model
Verhaege, K.; Roussel, P.J.; Groeseneken, G.; Maes, H.E.; Gieser, H.; Russ, C.; Egger, P.; Guggenmos, X.; Kuper, F.G.
Conference Paper
1994A CMD-only reproducible field degradation and its reliability aspect
Gieser, H.A.; Egger, P.; Reiner, J.C.; Herrmann, M.R.
Conference Paper
1994Compact electro-thermal simulation of ESD-protection elements
Russ, C.; Gieser, H.; Egger, P.; Irl, S.
Conference Paper
1994ESD protection elements during HBM stress tests - further numerical and experimental results
Russ, C.; Gieser, H.; Verhaege, K.
Conference Paper
1994ESD protection elements during HBM stress tests - further numerical and experimental results
Russ, C.; Gieser, H.; Verhaege, K.
Conference Paper
1994Influence of tester parasitics on "charged devive model"-failure thresholds
Gieser, H.A.; Egger, P.
Conference Paper
1994Survey on electrostatic susceptibility of integrated circuits
Gieser, H.; Ruge, I.
Conference Paper